Self-configurable amplifier circuit

ABSTRACT

An amplifier circuit is disclosed which receives signals that cause the amplifier to be configured in an asymmetrical mode or symmetrical mode, so that performance may be optimized in each mode.

FIELD OF THE INVENTION

The invention relates to the field of tuners. The invention also relatesto devices wherein such tuners are implemented, such as televisionreceivers, video recorders or decoder boxes. The invention moreparticularly relates to an amplifier circuit comprising:

a pre-amplifying stage,

an amplifying stage, and

identification means for identifying the configuration of the amplifyingstage.

PRIOR ART

Such an amplifier circuit is known from the PCT patent applicationpublished under publication no. WO 00/21193.

According to this patent application, when an amplifying stage 511 isconfigured so as to be in the asymmetrical mode, i.e. when differentoutputs of this amplifying stage are connected together, a commutator Swcontrolled by control means 53 connects one of the outputs O₂ of theamplifying stage 511 to ground. A configuration in an asymmetrical modeof an amplifying stage optimized for operation in the symmetrical modecauses a deterioration of the amplification characteristics. Themagnitude of this deterioration can be limited to some extent byconnecting one of the outputs of the amplifying stage to ground. In animproved variant, as shown in FIG. 2 of said patent application,commutation means 2513 comprise two commutators. When the amplifyingstage 2511 is configured so as to be in the symmetrical mode, a firstcommutator: SW 22 is open so that the gain of the amplifier circuit isdetermined by a first set of resistors R₁, R₂ and R₄. When theamplifying stage 2511 is configured so as to be in the asymmetricalmode, a single output branch of the amplifying stage is used, and it issuitable to increase the gain of said branch. For this purpose, thecommutator SW 22 is in the closed state and a resistor R₃ is introducedinto the circuit, thereby increasing the gain of the branch that isstill being used.

Said patent application does not indicate how the controller 53 iscontrolled so as to either activate or not activate the commutationmeans SW, SW₂₁, SW₂₂. Persons skilled in the art are also well aware ofthe fact that the modification of the amplifier circuit intended tolimit the deterioration of the amplification characteristics onlypalliates this deterioration, and that the correction is not the optimumthat can be achieved in the asymmetrical mode.

BRIEF DESCRIPTION OF THE INVENTION

It is an object of the invention to overcome the drawbacks describedhereinabove by providing an amplifier circuit which can suitably beconfigured, in a flexible manner, so as to be in the symmetrical orasymmetrical mode, the performance of the circuit being automaticallyoptimized irrespective of the mode of operation of the circuit resultingfrom its configuration.

Thus, in accordance with the invention, an amplifier circuit inaccordance with the opening paragraph is characterized in that itadditionally comprises adaptation means to configure the pre-amplifyingstage in such a manner that it supplies the amplifying stage with:

either two signals which are in phase opposition if the amplifying stageis configured so as to be in the symmetrical mode,

or two signals which are in phase if the amplifying stage is configuredso as to be in the asymmetrical mode.

By virtue of the invention, in either mode of operation, i.e. thesymmetrical or asymmetrical mode, the performance of the amplifiercircuit as regards gain, linearity and output impedance meets theexpectations of a circuit optimized for operation in said mode. Thus,unlike the prior art, it is not merely a limitation of the degradationin performance resulting from a configuration other than theconfiguration for which the amplifier circuit has been designed, butinstead an optimization of each one of the configurations.

In the amplifier circuit in accordance with the prior art, a part of theamplifying stage is deactivated during operation in the asymmetricalmode, the gain of the other part being then increased. In accordancewith the invention, the whole amplifying stage is used to full advantageto generate the output signal of the amplifier circuit, irrespective ofthe configuration chosen.

Thus, in its most general mode, the invention relates to a method ofoptimizing the operation of an amplifier circuit, comprising:

a pre-amplifying stage, and

an amplifying stage,

which method includes an identification step for identifying theconfiguration of the amplifying stage, characterized in that the methodadditionally comprises a configuration step for configuring thepre-amplifying stage, as a result of which the amplifying stage issupplied with:

either two signals which are in phase opposition if the amplifying stageis configured so as to be in the symmetrical mode,

or two signals which are in phase if the amplifying stage is configuredso as to be in the asymmetrical mode.

In accordance with an embodiment of the invention, the pre-amplifyingstage may comprise two pre-amplifiers, which are both arranged betweentwo inputs of the amplifier circuit and two inputs of the amplifyingstage, the adaptation means alternately activating one of the twopre-amplifiers and deactivating the other.

The first pre-amplifier amplifies the input signal in such a way thatthe signals present at each one of the outputs are in phase oppositionwith respect to one another. The second pre-amplifier amplifies theinput signal in such a way that the signals present at each one of theoutputs of the pre-amplifying stage are in phase.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages will be apparent from the description of an embodimentof the invention, which description is given with reference to theannexed drawings, wherein:

FIG. 1 is a functional diagram of a receiver of radioelectric signals,wherein the invention is implemented;

FIG. 2 is a functional diagram of a tuner included in such a receiver;

FIG. 3 is a functional diagram of an embodiment in accordance with theinvention;

FIG. 4 is an electrical circuit diagram of an embodiment of a part ofthe identification means for identifying the configuration of theamplifying stage;

FIG. 5 is an electrical circuit diagram of an embodiment of another partof identification means for identifying the configuration of theamplifying stage;

FIG. 6 is a synthesis diagram of FIGS. 3 to 5;

In each one of the drawings, like reference numerals refer to likeparts.

DESCRIPTION OF AN EMBODIMENT IN ACCORDANCE WITH THE INVENTION

FIG. 1 diagrammatically shows a receiver for receiving radioelectricsignals, for example a television receiver, which comprises, downstreamof an input stage, constituent in this example by an antenna 1:

an amplifier 2 receiving the antenna signal through one or severalpassband filters 3, and

a tuner 5 receiving, through the filters 4, a signal originating fromthe amplifier 2. The tuner 5 supplies an output signal having anintermediate frequency. Usually, a tuner doesn't comprise only a singlechain composed of the elements 2 through 4. A tuner often comprisesadditional chains, diagrammatically represented in this example byreference numerals 6 and 7. Each one of the chains can be tuned to aparticular frequency included in a band of operation of the chain. Theintermediate frequency IF at the output of the tuner 5 is always thesame. Its value generally lies between 30 and 60 MHz.

FIG. 2 diagrammatically shows a tuner 5 comprising a mixer 8 receiving,at an input 9, the amplified antenna signal and, at an input 10, asignal originating from a local oscillator 11. The frequency of theoscillator 11 is controlled by a phase-locked loop 12, which itself iscontrolled, through a bus 13, by a microcontroller 14. The output 15 ofthe mixer 8 conveys an intermediate frequency signal, which can betransmitted in one or several channels, for example, in the singlesideband (SSB). If there are several channels, the signal is introduced,for example, at a surface wave filter 16 which is intended to separatethe channels. In accordance with a first variant, which is generallyused in Europe, the surface wave filter 16 is a high-impedance filter,for example 500 Ω, and the introduction of the signal takes placethrough a passband filter 17. In accordance with a second variant, whichis more generally used in Asia and indicated by means of dashed lines,the output signal 15 of the mixer 8 is amplified by an amplifier 18before being introduced into the acoustic wave filter 16 having anoutput 20. One or several wall filters, such as the one bearingreference numeral 19, which is used for trapping certain frequencies,may be used for filtering the output signal 15. In the applicationdescribed hereinabove, the circuit in accordance with the invention isarranged downstream of the tuner 5.

FIG. 3 shows an amplifier circuit 50 in accordance with a particularembodiment of the invention, said amplifier circuit having two inputs20, 20′ and two outputs 28, 28′. The circuit 50 comprises apre-amplifying stage 41, two inputs of which are connected to inputs 20,20′ of the amplifier circuit, and two outputs 27, 27′ of which areconnected to two inputs of the amplifying stage 42 comprising twoamplifiers 22, 22′. The preamplifying stage 41 comprises a first and asecond pre-amplifier 31, 44 which are arranged in parallel between theinputs 20, 20′ and the outputs 27, 27′ of the pre-amplifying stage. Theoutputs of the first pre-amplifier 31 convey signals which are in phaseopposition.

The outputs of the second pre-amplifier 44 carry signals which are inphase. The two pre-amplifiers 31, 44 never operate simultaneously; theyoperate alternately according to the configuration of the amplifyingstage 42. The second pre-amplifier 44 is itself composed of two parts21, 21′.

Each part 31, 21 and 21′ comprises a long-tail pair of transistors (23,24); (23′, 24′); and (23″, 24″), respectively, the control terminals ofwhich are formed by the bases of said transistors, and an outputterminal of which is formed by the collector of one of the transistorsof the long-tail pair. The bases of the transistors 23, 23′ and 23″ areconnected to the input 20, while the bases of the transistors 24, 24′and 24″ are connected to the inputs 20′. As the control terminals of thelong-tail pairs (23′, 24′) and (23″, 24″) included in the secondpre-amplifier 44 are identically coupled for both long-tail pairs, theoutputs 27 and 27′ of the second pre-amplifier 44 supply current signalswhich are in phase. In addition, the gains of the long-tail pairs (23,24), (23′, 24′), (23″, 24″) included in the pre-amplifiers 31 and 44 canbe advantageously made variable so as to enable an increase of theflexibility of the amplifier circuit. This can be achieved by choosingvariable current sources to bias said long-tail pairs, according to atechnique which is well known to those skilled in the art Though, inthis example, bipolar-type transistors are employed, these transistorscan be substituted with MOS-type transistors, the grids of which wouldthen form the control terminals. The two amplifiers 22 and 22′ are usedsimultaneously irrespective of which one of the pre-amplifiers 31 or 44is activated.

The configuration of the pre-amplifying stage 41 is carried out asfollows: In the embodiment discussed herein, the first symmetricaloutput pre-amplifier 31 is selected by default Of course, it is alsopossible to select the second pre-amplifier 44 by default. Theconnection of outputs 28, 28′ of the amplifier circuit 50 in theshort-circuit configuration, i.e. in the asymmetrical mode, or to a loadimpedance, i.e. in the symmetrical mode, is most often definitivelyperformed by the manufacturer of the apparatus which incorporates saidamplifier circuit. The amplification circuit 50 is provided withidentification means 45 of the configuration as the amplifying stage 42,which identification means are parallel connected to a load impedance,not shown in the drawing, between the outputs 28 and 28′. Theidentification means 45 produce a so-called selection signal, the valueof which enables the presence of a weak load impedance to be identified,i.e. a load impedance value below a predetermined threshold, or thepresence of a standard load impedance corresponding to a situationwherein the amplifier circuit 50 is configured so as to be in thesymmetrical mode. The selection signal is transmitted to adaptationmeans 46. If the selection signal indicates that the amplifying stage 42is not configured to operate in the symmetrical mode, i.e. using thepre-amplifier 31 provided by default, then the adaptation means 46 areactivated by the selection signal. If the adaptation means areactivated, they cause the transistors (23, 24) of the firstpre-amplifier 31 to become deactivated, and the transistors (23′24′);(23″24″) of the second pre-amplifier 44 to become activated. Activationor deactivation of the transistors is obtained by, respectively,activating or deactivating the current sources biasing the transistors.

FIGS. 4 and 5 show an embodiment of identification means 45.

FIG. 4 shows detection means 60 included in the identification means 45.In FIG. 4, the amplifiers 22 and 22′ are shown, said amplifiers eachhaving an output resistor Rs 47, 47′ arranged between a point 51, 51′and the output 28, 28′ respectively. A load impedance RL is assumed tobe arranged between the two outputs 28 and 28′. The detection meansshown in FIG. 4 comprise a first and a second main branch 48 and 48′respectively. The first main branch 48 comprises three branches 52, 53and 54. An end of a branch 52 is connected to an output 55 of the branch48. Said branch comprises a transistor, the collector of which isconnected to the output 55, and the emitter of which is connected,through a resistor Rm, to the connection 51 opposite the output 28 of anoutput resistor 47 of the amplifier 22. A central branch 53 comprises atransistor arranged in a diode configuration, a collector connected tothe base, arranged in series with a resistor Rc arranged between thecollector of the transistor and a bias-voltage source, and in serieswith a resistor Rm arranged between the emitter of the transistor andthe output 28. A branch 54 is identical to the branch 52. The collectorof the transistor of the branch 54 is connected to the output 55 of thebranch 48, and the emitter is connected, through a resistor of value Rm,to the output 28′ of the amplifier 22′. The second main branch 48′ ofthese detection means 60 included in the identification means 45 and thebranch 48 are symmetrical with respect to an imaginary center point 0 ofthe load resistor RL, thereby dividing the load resistor RL in two halfresistors having a value RL/2 each. The resistor RL is intended toproduce an output voltage, referenced Vout, having a DC component,referenced Vout_(dc), and an AC component, referenced Vout_(ac). In anidle state, i.e. in the absence of the AC component Vout_(ac), thebranch 54 is a current mirror of the branch 53. If an AC componentVout_(ac) appears at the terminals of the load resistor RL, the resistorRm of the branch 54 is subjected to an additional voltage resulting inan additional current i′=Vout_(ac)/Rm With respect to the rest of theexplanation, it is to be noted that if Rc is much larger than Rm, theidle current i, which is equal to Vout_(ac)/(Rc+Rm), is much smallerthan i′. For example, if Rc=10 Rm, then i′ is more than ten times largerthan i. As a result, it is possible to disregard the idle current i inthe rest of the explanations. If it is assumed that RL/2 is equal to thesum of the output resistances Rs, then a current i″ present in thebranch 52 is equal to i′. In this case, the current at the output 55 ofthe branch 48 is zero. If it is assumed that RL is much larger than Rs,then the current i′ in the branch 54 is much larger than the current i″in the branch 52. In this case, the direction of the current at theoutput 55 is the same as that of the current i′ in the branch 54. Thesame result is obtained for the branch 48′. The current at the output55′ flows in the same direction as the current i′ in the branch 54′. IfRL is much smaller than Rs, which corresponds particularly to ashort-circuit between the outputs 28 and 28′the current i′ in the branch54 is smaller than the current i″ in the branch 52. In this case, at theoutput, there is a current that flows in the same direction as thecurrent i″ in the branch 52. This is also true for the branch 48′. Thus,depending on the relative value of the resistors RL and Rs, thedirection of flow of the current present at the output 55, 55′ of thebranches 48 and 48′ is either the same as or opposite to the directionof flow of the current at the output of the amplifiers 22, 22′. Acomparison between the direction of flow of the current at the output55, 55′ and the direction of flow of the current at the output of theamplifiers 22, 22′ indicates whether the amplifier circuit is connectedin the symmetrical mode or the asymmetrical mode. For a betterunderstanding of the circuit, some numerical values will be givenhereinbelow by way of example. The resistances Rm and Rc may be of theorder of 4 kΩ and 40 kΩ, respectively. If a load impedance of 500 Ω isconnected to two outputs 28, 28′ which are mutually short-circuited by ashort-circuit of 2 Ω, corresponding to a welding capacity of 1nanofarad, a current of 25 μA is obtained, for an amplitude of theoutput voltage of 100 mV, at the output 55, 55′, which is amplysufficient to activate logic circuits included in the adaptation means.

These values show that the output signal Vout is not in the leastdisturbed by the detection means 60.

FIG. 5 shows selection means 70 included in the identification means 45.These selection means are intended to generate a current, forming theselection signal, the direction of which is always the same and dependsonly on the relative values of the resistances RL and Rs. This circuitcomprises two outputs K, K′. Depending on the relative values of theresistances RL and Rs, only one of these two outputs is energized. Theselection means 70 comprise a GILBERT cell 59 including a first and asecond pair 61, 61′ of NPN transistors 57, 58 and 57′, 58′ respectively.The selection means additionally comprise a PNP transistor 63 arrangedin a diode configuration, the base and the collector of which areconnected to an output 55 of the above-described detection means. TwoPNP transistor 64, 65 are arranged in a current-mirror configurationwith the transistor 63. The collector of the transistor 64 is connectedto a collector of an NPN transistor 66 which is arranged in a diodeconfiguration. The collector of the PNP transistor 65 is connected tothe common emitter of the second pair 61′ of the transistors 57′, 58′ ofthe GILBERT cell 59. The selection means 70 comprise, in a symmetricalmanner, a PNP transistor 63′ arranged in a diode configuration, the baseand the collector of which are connected to another output 55′ of thedetection means described with respect to FIG. 4. Two transistors 65′and 64′ are arranged in a current-mirror configuration with thetransistor 63′. The collector of the PNP transistor 64′ is connected tothe collector of an NPN transistor 66′ arranged in a diodeconfiguration. The collector of the transistor 65′ is connected to thecommon emitters of the transistors 57, 58 of the first pair 61 of theGILBERT cell 59. The collectors of a first transistor 57, 57′ of eachpair 61, 61′ are connected to a point K forming an output of the circuit70, and the collectors of a second transistor 58, 58′ of each pair 61,61′ are connected to a point K′ forming another output of the circuit70. The common emitters of the transistors of each pair 61, 61′ areconnected to, respectively, the NPN transistors 67, 67′ said transistors67, 67′ being arranged in a current-mirror configuration with thetransistors 66 and 66′, respectively. The base of the first transistor57 of the pair 61′ and the base of the second transistor 58′ of the pair61′ are jointly connected to the output 28 of the amplifying stage. Thebase of the second transistor 57′ of the pair 61′ and the base of thefirst transistor 58 of the first pair 61 are jointly connected to theoutput 28′ of the amplifying stage. Resistors, not shown in the drawing,may be inserted between the output terminals 28, 28′ and the bases ofthe transistors (57, 58′) and (57′, 58), respectively, to improve thelinearity of the GILBERT cell 59.

The operation of the selection means 70 is as follows: If it is assumedthat a current signal is supplied by the outputs 55, 55′ of thedetection means 60, then only one of the outputs K or K′ supplies acurrent. If, at the time of a subsequent alteration, the current signalsupplied by the outputs 55, 55′ of the detection means 60 changesdirection, the biasing of the bases of the transistors 57, 58′ and57′,58 of the GILBERT cell received from the outputs 28, 28′ are alsoinversed, so that the current at the output of the cell 59 is present atthe same output K or K′ than at the time of the preceding alternation.Thus, depending on whether the load resistance RL present between theoutputs 28 and 28′ is larger than the output resistance Rs of theamplifiers 22, 22′, or, conversely, smaller than said output resistanceRs of the amplifiers 22, 22′ one of the outputs K or K′ supplies acurrent, for example output K if RL<<Rs, or output K′ in the oppositecase.

FIG. 6 diagrammatically shows again the assembly shown in FIG. 3 toillustrate the connections between the different parts of the amplifiercircuit 50. The outputs 51, 28, 51′, 28′ of the stage 42 form inputs forthe detection means 60 included in the identification means 45. Theselection means 70, which form part of the identification means 45,receive the current originating from the outputs 55, 55′ of thedetection means 60. The outputs K, K′ of the selection means 70 generatethe selection signal, which is applied to a memory flip-flop included inthe adaptation means 46. Outputs Q and Qnot of this memory flip-flopsupply activation or deactivation signals intended to be applied inreturn to the pre-amplifying stage 41 of the amplifier circuit 50. If,in the example described hereinabove, the selection signal is such thatthe output K is activated and the output K′ is deactivated, this meansthat the value of the load resistance RL is very small as compared tothat of the resistances Rs, i.e. the amplifying stage 42 is configuredso as to be in the asymmetrical mode. The outputs Q and Qnot of theadaptation means 46 then enter the active or inactive state,represented, for example, by the logic levels 1 and 0, respectively,thereby activating the current sources biasing the long-tail pairs ofthe second pre-amplifier 44 and deactivating the long-tail pair of thefirst pre-amplifier 31.

What claim is:
 1. An amplifier circuit comprising: a preamplifyingstage; an amplifying stage, and identification means for identifying theconfiguration of the amplifying stage, which circuit is characterized inthat it additionally comprises adaptation means to configure thepre-amplifying stage in such a manner that it supplies the amplifyingstage with: either two signals which are in phase opposition if theamplifying stage is configured so as to be in the symmetrical mode, ortwo signals which are in phase if the amplifying stage is configured soas to be in the asymmetrical mode wherein said pre-amplifying stagecomprises two pre-amplifiers, which are both arranged between two inputsof the amplifier circuit and two inputs of the amplify stage, theadaptation means alternately activating one of the two pre-amplifiersand deactivating the other.
 2. An amplifier circuit as claimed in claim1, characterized in that the pre-amplifying stage includes a firstpreamplifier comprising two transistors forming a long-tail pair, havingcontrol terminals which are connected to inputs of the amplifiercircuit.
 3. An amplifier circuit as claimed in claim 1, characterized inthat the pre-amplifying stage includes a second preamplifier comprisingfour transistors which, arranged two-by-two, form a first and a secondlong-tail pair, having control terminals which are connected in parallelto inputs of the amplifier circuit, each long-tail pair having an outputconnected to one of the inputs of the amplifier stage.
 4. An amplifiercircuit as claimed in claim 1, characterized in that the identificationmeans of the amplifying stage configuration comprise detection meansconnected to the outputs of said amplify stage, said detection meanshaving at least one output intended to supply a current whose directionis determined univocally by the direction of an output current generatedby the amplifier circuit.
 5. An amplifier circuit as claimed in claim 1,characterized in that identification means of the amplifying stageconfiguration comprise selection means connected to detection means andhaving two outputs intended to be energized alternately according to thedirection of the current supplied by the outputs of the detection means.6. An amplifier circuit as claimed in claim 1, characterized in that theadaptation means comprise a flip-flop intended to store informationprovided by the identification means, a logic output of said flip-flopbeing coupled to the pre-amplifying stage.
 7. A tuner characterized inthat it includes an amplifier circuit as claimed in claim
 1. 8. Areceiver for receiving radioelectric signals, characterized in that itincludes a tuner as claimed in claim
 7. 9. A method of optimizing theoperation of an amplifier circuit comprising a preamplifying stage, andan amplifying stage, which method comprises an identification step foridentifying the amplifying stage configuration, characterized in thatthe method additionally includes a configuration step to configure thepre-amplifying stage in such a manner that it supplies the amplifyingstage with: either two signals which are in phase opposition if theamplifying stage is configured so as to be in the symmetrical mode, ortwo signals which are in phase if the amplifying stage is configured soas to be in the asymmetrical mode the configuration step includingalternately activating one of two pre-amplifiers and deactivatinganother of said two pre-amplifiers.